Please use this identifier to cite or link to this item: http://dl.pgu.ac.ir/handle/Hannan/114265
Title: A 2.7uW/Mips, 0.88GOPS/mm^2 Distributed Processor for Implantable Brain Machine Interfaces
Issue Date: 10-Aug-2016
Publisher: IEEE
Description: This paper presents a scalable architecture in 0.18u m CMOS for implantable brain machine interfaces (BMI) that enables micro controller flexibility for data analysis at the sensor interface. By introducing more generic computational capabilities the system is capable of high level adaptive function to potentially improve the long term efficacy of invasive implants. This topology features a compact ultra low power distributed processor that supports 64-channel neural recording system on chip (SOC) with a computational efficiency of 2.7uW/MIPS with a total chip area of 1.37mm2. This configuration executes 1024 instructions on each core at 20MHz to consolidate full spectrum high precision recordings from 4 analogue channels for filtering, spike detection, and feature extraction in the digital domain.
URI: http://dl.pgu.ac.ir/handle/Hannan/114265
Other Identifiers: http://hdl.handle.net/10044/1/40782
EP/K015060/1
RES/0560/7386 & EFXD12018
EP/M020975/1
Type Of Material: OTHER
Appears in Collections:Electrical and Electronic Engineering

Files in This Item:
Click on the URI links for accessing contents.


Items in HannanDL are protected by copyright, with all rights reserved, unless otherwise indicated.