Please use this identifier to cite or link to this item: http://dl.pgu.ac.ir/handle/1853/5076
Title: Automated Bus Generation for Multi-processor SoC Design
Keywords: System-on-a-Chip (SoC);Bus architecture;Design space exploration;Bus generation;Computer-aided design;Integrated circuits Very large scale integration Design and construction
Issue Date: 12-Jul-2004
Publisher: Georgia Institute of Technology
Description: In the design of a multi-processor System-on-a-Chip (SoC), the bus architecture typically comes to the forefront because the system performance is not dependent only on the speed of the Processing Elements (PEs) but also on the bus architecture in the system. An efficient bus architecture with effective arbitration for reducing contention on the bus plays an important role in maximizing performance. Therefore, among many issues of multi-processor SoC research, we focus on two issues related to the bus architecture in this dissertation. One issue is how to quickly and easily design an efficient bus architecture for an SoC. The second issue is how to quickly explore the design space across performance influencing factors to achieve a high performance bus system. The objective of this research is to provide a Computer-Aided Design (CAD) tool with which the user can quickly explore System-on-a-Chip (SoC) bus design space in search of a high performance SoC bus system. From a straightforward description of the numbers and types of Processing Elements (PEs), non-PEs, memories and buses (including, for example, the address and data bus widths of the buses and memories), our Bus Synthesis tool, called BusSynth, generates a Register-Transfer Level (RTL) Verilog Hardware Description Language (HDL) description of the specified bus system. The user can utilize this RTL Verilog in bus-accurate simulations to more quickly arrive at an efficient bus architecture for a multi-processor SoC. The methodology we propose gives designers a great benefit in fast design space exploration of bus systems across a variety of performance influencing factors such as bus types, PE types and software programming styles (e.g., pipelined parallel fashion or functional parallel fashion). We also show that BusSynth can efficiently generate bus systems in a matter of seconds as opposed to weeks of design effort to integrate together each system component by hand. Moreover, unlike the previous related work, BusSynth can support a wide variety of PEs, memory types and bus architectures (including a hybrid bus architecture) in search of a high performance SoC.;Ph.D.;Committee Chair: Mooney, Vincent J.; Committee Member: Benkeser, Paul J.; Committee Member: Davis, Jeffrey A.; Committee Member: Starner, Thad; Committee Member: Yalamanchili, Sudhakar
URI: https://smartech.gatech.edu/handle/1853/5076
Type Of Material: OTHER
Appears in Collections:College of Engineering (CoE)

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