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|Title:||Oscillation Control in CMOS Phase-Locked Loops|
|Keywords:||Charge pump;PLL;Phase-locked loops;Mixed-signal circuits;Voltage-controlled oscillators;Digital electronics;Digital-to-analog converters;Metal oxide semiconductors, Complementary|
|Publisher:||Georgia Institute of Technology|
|Description:||Recent advances in voltage-controlled oscillator (VCO) design and the trend of CMOS processing indicate that the oscillator control is quickly becoming one of the forefront problems in high-frequency and low-phase-noise phase-locked loop (PLL) design. This control centric study explores the limitations and challenges in high-performance analog charge-pump PLLs when they are extended to multiple gigahertz applications. Several problems with performance enhancement and precise oscillator control using analog circuits in low-voltage submicron CMOS processes, coupled with the fact that analog (or semi-digital) oscillators having various advantages over their digitally controlled counterparts, prompted the proposal of the digitally-controlled phase-locked loop. This research, then, investigates a class of otherwise analog PLLs that use a digital control path for driving a current-controlled oscillator. For this purpose, a novel method for control digitization is described where trains of pulses code the phase/frequency comparison information rather than the duration of the pulses: Pulse-Stream Coded Phase-Locked Loop (psc-PLL). This work addresses issues significant to the design of future PLLs through a comparative study of the proposed digital control path topology and improved cutting-edge charge-pump PLLs.;Ph.D.;Committee Chair: Brooke, Martin; Committee Member: Cressler, John D.; Committee Member: Degertekin, Levent; Committee Member: DeWeerth, Stephen P.; Committee Member: Hasler, Paul E.|
|Type Of Material:||OTHER|
|Appears in Collections:||College of Engineering (CoE)|
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