Please use this identifier to cite or link to this item: http://dl.pgu.ac.ir/handle/1853/4764
Title: A Broadband Passive Delay Line Structure in 0.18 Micron CMOS For A Gigabit Feed Forward Equalizer
Keywords: Passive equalization;Passive delay lines;Inductor modeling
Issue Date: 1-Nov-2004
Publisher: Georgia Institute of Technology
Description: This project focusses on the design of a high speed passive delay line for use in a Feed Forward Equalizer (FFE). The FFE is used to equalize a 20 Gbp/s throughput PAM-4 signal after transmission through a 20-inch FR4 backplane channel. Inductor electromagnetic simulations are used to design an inductor for use in the passive delay line and a lumped element inductor model is presented. Measurement results show performance of the delay line at 10 GSym/s.;M.S.;Committee Chair: Dr. Joy Laskar; Committee Member: Dr John Papapolymerou; Committee Member: Dr Manos Tentzeris
URI: https://smartech.gatech.edu/handle/1853/4764
Type Of Material: Thesis
Appears in Collections:College of Engineering (CoE)

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